That gigabyte of paperwork turns out to be the gift that holds the gift back. As we speak, AMD’s alternative info contains AMD’s long-term plan for graphics with Ryzen and some early details about Genoa. Readers should remember that leaks are by definition unofficial and that documentation may change and be up to date over time.
As for the details of low-level Genoa, the purpose of the background material is not to present an exhaustive summary of the variations between Zen Three and Zen four. A fair amount of kernel knowledge has been gleaned from the feature-level documentation and a few high-level datasheets. Such information could be legitimate but contextually incomplete. Any given technical document will focus on the improvements and capabilities of the processor in relation to the particular topic at hand, implying that the collective details on the options are widely distributed and take more time to study.
We’ll talk about the GPU aspect of the issues first and then pivot to the CPU.
This document means that all three forms of the Socket AM5 processor will ship with integrated graphics, although the aptitude is unlikely to be provided on every SKU. AMD might consider taking a page from Intel’s ebook and delivering a collection of non-GPU chips at costs barely lower than GPU-equipped variants. Of the three processor varieties, only one – presumably the desktop processor household – will provide 28 full PCIe lanes. The two opposing variants are limited to only 20 lanes. The difference in the number of households apparently points to desktop and laptop processors, with a low-end desktop variant configured in addition, just like the laptop chip.
A necessary level is that AMD might already have a chart very similar to this for products based on Zen Three. Suppose AMD finally delivers a low-end APU with 4 Zen Three cores and Vega or RDNA2 graphics. If this chip had been limited to 20 PCIe lanes, Zen Three’s theoretical product configuration would match what has been proven for Zen Four in the home scene. AMD’s cellular processors carry integrated graphics at all times, and the 5600G and 5700G have added Vega support to the six-core and eight-core markets.
We’re not claiming that different websites have spurious reports – we typically rely on AMD to add graphics to additional desktop and laptop products in general – but this news webpage doesn’t specifically claim that the company will achieve this with Zen four. The suggested L3 cache sizes of 16MB to 32MB are the same as the chips found in the 5700G and 5800X homes, respectively.
V-Cache will not be discussed here either. This does not imply that AMD will remove V-Cache from Zen Four. This may imply that the company did not finalize its V-Cache plans, that this document was written before those plans were made, or that the information was unrelated to the topic mentioned here.
Our personal premise is that the immediate inclusion of V-Cache in processors is perhaps a precursor to the subsequent integration of a GPU core cluster. Stacking a large L3 cache on top of the chip and allowing the GPU to use it will undoubtedly improve efficiency by relieving the stress of memory bandwidth. AMD has claimed it could potentially scale the previous 64MB V-Cache. There are some similarities to Intel’s 2013 Crystal Properly, but AMD claims that V-Cache can deliver 2TB / s memory bandwidth. Intel’s Crystal Properly was die-mounted but unpacked and simply offered 100 Gb / s of bandwidth. A sufficiently giant L3 shared by each CPU and GPU can allow the GPU to outperform any earlier AMD built-in response, providing a number of the benefits of a large interface like HBM at (presumably) a lower value.
Details of Genoa on the lower floor
Chips and Cheese also went digging through the Genoa documentation to research architectural improvements for Zen 4 over Zen Three. Genoa will generally support VNNI and AVX-512 directions, with an implementation similar to Ice Lake Server as long as full directions are supported. Chips and Cheese thinks it’s possible that Zen Four will provide both a single 1 × 512-bit FMA or a pair of 256-bit models that can be grouped together to help 512-bit math. Two floating-point models would allow Zen 4 to compete with Intel in AVX-512, while a single 512-bit unit would provide increased compatibility and efficiency in some cases without incurring the same power value. AMD previously applied AVX2 support with 128-bit registers, so AVX-512 with 256-bit registers would not be unprecedented.
Here is the overview:
There aren’t many tweaks here, although the extended L2 and larger DTLB are welcome. Mixed with AVX-512 support and Genoa’s intensive support tweaks for storage class memory, the chip’s server model will contain many improvements over Zen Three. The fact that we don’t see evidence of additional tweaks in this document may imply that Zen Four is an iterative improvement on Zen Three, or it could imply that the information is in different documents that address different facets of the chip. If AMD had hypothetically launched a Zen Four with a modest IPC improvement, a few hundred MHz of additional clock, AVX-512 support, and an earlier model from Infinity Material, it would hit all the classes that collectively justify calling a CPU a new architectural overhaul on what has happened before.
In other words: don’t conclude that Genoa isn’t much different from Zen Three on the idea of some paperwork. While it is true that AMD has largely focused on getting the 5nm transition rather than implementing new options, there is still plenty of time before the Zen 4 ships to learn more about the heart.
Chips and Cheese has an extra piece of Zen Four’s implementation of storage class memory, so take a look at them if you want to learn more on the subject. It’s fascinating not to talk about V-Cache in these stories, but the concept that AMD would remove the feature once applied can be odd. AMD claims it could potentially increase 1.15x from additional L3. If he removes this L3 in future designs, he must both take action by designing a processor that does not take advantage of it, or by designing a processor that is such a bounce in the clock and / or the IPC. , he doesn’t want the cache to meet AMD’s efficiency goals. Neither is unimaginable. However, AMD is unlikely to tackle the difficulty of building an L3 cache for future Zen Three chips just to remove it for Zen Four.